In recent years, Field Effect Transistors (FETs) including gallium nitride (GaN) nitride semiconductor have been actively developed to serve as high-frequency and high-power devices. GaN is mixed with aluminum nitride (AlN), indium nitride (InN), and the like to generate various mixed crystals.
In particular, a heterojunction in a nitride semiconductor has characteristics that spontaneous polarization or piezoelectric polarization causes highly-concentrated carriers (2 Dimensional Electron Gas (2DEG)) on the junction surface even if the nitride semiconductor is undoped. As a result, if an FET comprises nitride semiconductor, the FET is likely to be a depletion-mode (normally-on) transistor and it is difficult to cause the FET to have enhancement-mode (normally-off) properties. However, the most of devices used in present power electronics markets are normally-off devices, and the normally-off devices are highly demanded also for FETs comprising GaN nitride semiconductor.
A normally-off FET can be formed, for example, by digging a gate part to shift a threshold voltage to a positive voltage. It has also be known that an FET is manufactured on a plane (10-12) of a sapphire substrate to prevent polarization of electric field in a crystal growth direction of the nitride semiconductor. Furthermore, a Junction Field Effect Transistor (JFET) in which a p-type GaN layer is provided to a gate part is proposed as a potential structure serving as a normally-off FET (for example, refer to Patent Literature 1). In the JFET structure, piezoelectric polarization occurred on a heterointerface between a channel layer made of undoped GaN and a barrier layer made of AlGaN is cancelled by piezoelectric polarization occurred on a heterointerface between a barrier layer made of AlGaN and a p-type GaN layer. This structure can reduce the concentration of 2DEG in the p-type GaN layer immediately under the gate part. As a result, the normally-off properties can be offered. Furthermore, if a pn junction having a greater built-in potential than that of a Schottky junction is used as a gate, there are advantages that a rising voltage at the gate is increased and a gate leakage current is reduced even if a positive gate voltage is applied.
However, the conventional JFET has a problem that a so-called reverse transfer capacitance (expressed also as a mirror capacitance, a feedback capacitance, Cgd, or Crss) is large. The increase of the reverse transfer capacitance causes serious problems in a power transistor applied with a high drain voltage, such as inhibition of a high-speed operation and damages caused by erroneous turn-on.
In order to suppress the increase of Cgd, Patent Literature 2 discloses, for example, that a Schottky electrode having a source potential is provided between a gate electrode and a drain electrode of a GaN FET to prevent coupling of capacitance (Cgd) between the gate electrode and the drain electrode.